The present invention relates, in general, to the field of systems and methods of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line. More particularly, the present invention relates to a technique for compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line of especial utility in conjunction with a delay locked loop (xe2x80x9cDLLxe2x80x9d) circuit such as those utilized in double data rate (xe2x80x9cDDRxe2x80x9d) dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices, static random access memory (xe2x80x9cSRAMxe2x80x9d) devices, integrated circuit (xe2x80x9cICxe2x80x9d) processors and other IC devices.
DDR DRAM device functionality is specified by a Joint Electron Devices Engineering Counsel (xe2x80x9cJEDECxe2x80x9d) standard and such memories are able to achieve this effective doubling of the device""s bandwidth by inclusion of DLL circuitry to achieve synchronization of data accesses at a point in time to enable the reading of data on both the rising and falling edges of each clock cycle.
In such DLL circuits, a phase detector is utilized to determine the relative phase between two clock signals, such as the system clock and synchronization (xe2x80x9csyncxe2x80x9d) clock signal in a DDR memory device. In any event, the DLL is operational to adjust the control voltages (which, in a complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) implementation may be denominated xe2x80x9cVRxe2x80x9d for the control of N-channel devices and xe2x80x9cVCxe2x80x9d for control of P-channel devices) applied to a voltage controlled delay line until the two clock signals are perfectly in phase. Generally, a fast/slow latch circuit is used to generate a pulse on one of the DLL circuit latched signal lines when a delay adjustment is required to implement small adjustments to the control voltages.
In a conventional DLL circuit, the relationship between VR (and VC) and the delay through the voltage controlled delay line is very non-linear due at least in part to the non-linear gate-to-source characteristics of the transistors involved. For example, at low values of VR (which corresponds to relatively long delays through the delay line) the change in delay can be much larger for a given change in VR than is the case with relatively higher values of VR. On the other hand, if the increments of change in VR are made substantially constant, this can lead to significantly more xe2x80x9cjitterxe2x80x9d (the cycle by cycle changes in frequency of the signal) when the delay is long because the changes in VR then result in too much change in the delay.
Further, depending on the frequency of the DLL clock, the delay through the delay line can be one or multiple clock periods long. Consequently, the phase detector may actually be initiating changes in VR before the effect of a previous change is fully manifested in the sync clock phase. This lag effect then further adds to the jitter and, while implementing very small fixed increments of change in VR will somewhat ameliorate this problem, the phase locking time of the DLL circuit will then be made too long.
Disclosed herein is a system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line which effectively renders the incremental changes in the control voltages (e.g. VR) for each correction a function of the control voltage itself. In this manner, the change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter. Since the smallest corrections to be made will occur when VR is much lower than its initial value, the majority of the corrections made in moving from the initialization point to the final lock point in the DLL loop will be much larger than the final corrections thereby resulting in only minimally slower locking times than would otherwise be the case. Notwithstanding, it should also be noted that the changes in delay become inherently smaller if the lock point is at a higher VR value.
In accordance with the technique disclosed herein, the delay in the DLL loop is a function of the control voltage VR and this delay monotonically increases as the voltage level of VR decreases from its maximum value to its minimum value. Concomitantly, the incremental changes made in the voltage level of VR as a function of VR (the step size of VR=f(VR)) to effectuate the changes in delay monotonically decrease as the voltage level of VR decreases.
Particularly disclosed herein is a method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line and a means for implementing the method which comprises the steps of: providing at least one control voltage having an initial level thereof to the voltage controlled delay line; implementing a series of changes in the control voltage level; and controlling the series of changes in the control voltage level such that a difference between successive ones of the control voltage levels increase as said control voltage levels become greater and decrease as said control voltage levels become lower.
Also particularly disclosed herein is a circuit comprising a voltage controlled delay line and a delay voltage control circuit for supplying at least one control voltage to the voltage controlled delay line, the delay voltage control circuit being operative to control a level of the at least one control voltage such that a difference between successive levels in the control voltage level increase as said control voltage levels become greater and decrease as said control voltage levels become lower.